Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip †
dc.contributor.author | Goksoy, A.A. | |
dc.contributor.author | Hassan, S. | |
dc.contributor.author | Krishnakumar, A. | |
dc.contributor.author | Marculescu, R. | |
dc.contributor.author | Akoglu, A. | |
dc.contributor.author | Ogras, U.Y. | |
dc.date.accessioned | 2024-04-02T17:13:54Z | |
dc.date.available | 2024-04-02T17:13:54Z | |
dc.date.issued | 2023-10-17 | |
dc.identifier.citation | Goksoy, A.A.; Hassan, S.; Krishnakumar, A.; Marculescu, R.; Akoglu, A.; Ogras, U.Y. Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip. J. Low Power Electron. Appl. 2023, 13, 56. https://doi.org/10.3390/ jlpea13040056 | |
dc.identifier.issn | 2079-9268 | |
dc.identifier.doi | 10.3390/jlpea13040056 | |
dc.identifier.uri | http://hdl.handle.net/10150/672134 | |
dc.description.abstract | Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively. © 2023 by the authors. | |
dc.language.iso | en | |
dc.publisher | Multidisciplinary Digital Publishing Institute (MDPI) | |
dc.rights | © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). | |
dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | |
dc.subject | domain-specific SoC | |
dc.subject | DSSoC | |
dc.subject | policy switching | |
dc.subject | runtime classification | |
dc.subject | task scheduling | |
dc.title | Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip † | |
dc.type | Article | |
dc.type | text | |
dc.contributor.department | Department of Electrical and Computer Engineering, University of Arizona | |
dc.contributor.department | Department of Electrical and Computer Engineering, University of Arizona | |
dc.identifier.journal | Journal of Low Power Electronics and Applications | |
dc.description.note | Open access journal | |
dc.description.collectioninformation | This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu. | |
dc.eprint.version | Final Published Version | |
dc.source.journaltitle | Journal of Low Power Electronics and Applications | |
refterms.dateFOA | 2024-04-02T17:13:54Z |