An Ecosystem for Evaluating Domain-Specific System on Chip (DSSoC) Devices: Productive Application Deployment and Scheduling Perspectives

Abstract

The continued stagnation of transistor scaling is leading to a resurgence of research into foundational assumptions in computer architecture design, leading to what Hennesey and Patterson term ``a new golden age for computer architecture''. Domain Specific System-on-a-Chip (DSSoC) devices are one promising avenue by which this architectural innovation is manifesting to meet tomorrow's computational demands, but they are burdened by the numerous challenges of building devices that leverage widespread heterogeneity. This dissertation contributes to addressing these challenges through a uniquely holistic view of heterogeneous runtime design with respect to resource management and scheduling, accelerator integration, and compilation frameworks. The presentation opens with a discussion of resource management policies and presents novel approaches towards adapting list scheduling algorithms, commonly applied only within HPC contexts, to SoC scale systems via comprehensive simulation-based studies. Following this, the presentation features a broad overview of the iterative design, development, and evaluation of a novel DSSoC runtime, ``CEDR'' -- an open source, unified compilation and runtime framework for DSSoC architectures that allows applications, scheduling heuristics, and accelerators to be co-designed in a cohesive manner. Taken together, it presents a uniquely holistic perspective on the design of environments for exploring the boundaries of productive application deployment, scheduling algorithm development, and hardware configuration analysis for heterogeneous architectures.