An Emulation Framework for Exploring Domain-Specific SoCs in the Trade Space of Hardware Configuration, Resource Management and Workload Composition

Abstract

System designers are continuously exploring design methodologies that harness increased levels of heterogeneity towards pushing the boundaries of achievable performance gains. Optimizing a heterogenous computing system is a multi-dimensional and complex design space exploration problem particularly in scenarios where algorithms, data types, and processing resources and their availability vary dynamically. This dissertation addresses the need for productive application development and deployment on heterogenous systems through two open-source ecosystems with an aim to make emerging computing systems accessible for users. We have developed CEDR, an open-source, unified compilation, and runtime framework designed for heterogeneous systems. We introduce a new approach to runtime system development that reduces the overhead dedicated to managing system resources from 2000 cycles scale to 30 cycles scale, making CEDR practical for deployment in real-time embedded systems. This framework empowers users to develop, compile, and deploy applications on off-the-shelf heterogeneous computing platforms seamlessly, eliminating the need for users to possess specialized hardware expertise throughout the process. Furthermore, it facilitates the evaluation of resource management strategies and validation of hardware configurations within a single, cohesive framework. Importantly, this framework is portable across a wide range of Linux-based systems, ensuring that effort to migrate across systems is minimal for all developers involved. Its utility has been successfully tested by numerous partners from both industry and academia. With the same motivation we have developed RANC, an open-source highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the utility of RANC through co-design of a neuromorphic architecture and error correction code implementation. Through FPGA based emulation using Xilinx Zynq ZCU102 MPSoC, we show that the proposed implementation reduces energy consumption by 31% with a negligible increase in resource usage while achieving the same error correction performance.The implementation of the CEDR and RANC ecosystems pave the way towards design, emulation and evaluation of novel heterogeneous computing platforms consisting of neuromorphic processors that are integrated with heterogenous systems composed of a wide range of accelerators and general purpose processors. These platforms would enable users to meet the stringent performance and energy-efficiency requirements of emerging applications, both of cognitive and non-cognitive nature. Especially for application domains such as IoT, where edge devices with small weight and power are required to perform frequent intelligent sensing and inference types of operations, these ecosystems provide an avenue for rapid, dynamic and energy-efficient deployment and exploration of a wide range of applications, including but not limited to Spiking Neural Networks.