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    FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond

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    oe-31-6-10936.pdf
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    Author
    Yang, M.
    Pan, Z.
    Djordjevic, I.B.
    Affiliation
    Department of Electrical and Computer Engineering, The University of Arizona
    Issue Date
    2023-03-10
    
    Metadata
    Show full item record
    Publisher
    Optica Publishing Group (formerly OSA)
    Citation
    Mingwei Yang, Ziwen Pan, and Ivan B. Djordjevic, "FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond," Opt. Express 31, 10936-10946 (2023).
    Journal
    Optics Express
    Rights
    © 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement.
    Collection Information
    This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.
    Abstract
    We evaluate the burst-error performance of the regular low-density parity-check (LDPC) code and the irregular LDPC code that has been considered for ITU-T's 50G-PON standard via experimental measurements in FPGA. By using intra codeword interleaving and parity-check matrix rearrangement, we demonstrate that the BER performance can be improved under ∼44-ns-duration burst errors for 50-Gb/s upstream signals. © 2023 Optica Publishing Group.
    Note
    Immediate access
    ISSN
    1094-4087
    PubMed ID
    37157628
    DOI
    10.1364/OE.477546
    Version
    Final Published Version
    ae974a485f413a2113503eed53cd6c53
    10.1364/OE.477546
    Scopus Count
    Collections
    UA Faculty Publications

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