FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond
Affiliation
Department of Electrical and Computer Engineering, The University of ArizonaIssue Date
2023-03-10
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Show full item recordPublisher
Optica Publishing Group (formerly OSA)Citation
Mingwei Yang, Ziwen Pan, and Ivan B. Djordjevic, "FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond," Opt. Express 31, 10936-10946 (2023).Journal
Optics ExpressRights
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement.Collection Information
This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.Abstract
We evaluate the burst-error performance of the regular low-density parity-check (LDPC) code and the irregular LDPC code that has been considered for ITU-T's 50G-PON standard via experimental measurements in FPGA. By using intra codeword interleaving and parity-check matrix rearrangement, we demonstrate that the BER performance can be improved under ∼44-ns-duration burst errors for 50-Gb/s upstream signals. © 2023 Optica Publishing Group.Note
Immediate accessISSN
1094-4087PubMed ID
37157628Version
Final Published Versionae974a485f413a2113503eed53cd6c53
10.1364/OE.477546
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